IBM Triples Chip Memory Capacity
IBM Triples Chip Memory Capacity
February 15, 2007: IBM is looking to change the face of networking, gaming and multi-media applications by unveiling new technology that triples the memory stored on computer chips.
IBM’s latest announcement sounds like good news for the state of performance, speed and energy consumption. By embedding dynamic random access memory (eDRAM) IBM says it has achieved record access speeds while at the same time limiting energy consumption.
It’s a new method for placing memory on a chip by using dynamic RAM (DRAM) instead of static RAM (STRAM.) The new method will allow the chip to use one fifth of its usual electrically consumption and store data in one third of the area.
The announcement come after much anticipation and was made through the release of a paper earlier this morning at the International Solid State Circuits conference in San Francisco.
Subramanian Iyer, an IBM engineer and director of 45-nanometer technology, says that IBM is effectively doubling microprocessor performance beyond what can currently be achieved from classical scaling alone. This process will ultimately improve performance for applications involving graphic data such as networking, gaming and multi-media.
“As semiconductor components have reached the atomic scale, design innovation at the chip level has replaced materials science as a key factor in continuing Moore’s Law,” he said, referring to a technology ‘law’ that chip capacity doubles every two years.
IBM is looking to make the technology available in its 45-nanometer microprocessor line in early 2008. Somewhere between 24MB and 48MB of on-chip cache memory will end up in the new processors.